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64k x 4 static ram with separate i/o cy7c192 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-05047 rev. ** revised august 24, 2001 92 features ? high speed ?12 ns cmos for optimum speed/power low active power ? 880 mw low standby power ? 220 mw ttl-compatible inputs and outputs automatic power-down when deselected functional description the cy7c192 is a high-performance cmos static ram orga- nized as 65,536 x 4 bits with separate i/o. easy memory ex- pansion is provided by active low chip enable (ce ) and three-state drivers. it has an automatic power-down feature, reducing the power consumption by 75% when deselected. writing to the device is accomplished when the chip enable (ce ) and write enable (we ) inputs are both low. data on the four input pins (i 0 through i 3 ) is written into the memory location specified on the address pins (a 0 through a 15 ). reading the device is accomplished by taking the chip enable (ce ) low while the write enable (we ) remains high. under these conditions the contents of the memory location specified on the address pins will appear on the four data output pins. the output pins stay in high-impedance state when write en- able (we ) is low, or chip enable (ce ) is high. a die coat is used to insure alpha immunity. gnd 28 logic block diagram pin configurations 1024 x 64 x 4 array a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 10 a 11 a 13 a 12 a 14 a 15 column decoder row decoder sense amps power down we o 0 ce o 1 o 2 o 3 4 5 6 7 8 9 10 321 27 1314151617 26 25 24 23 22 21 20 1 2 3 4 5 6 7 8 9 10 11 14 15 16 20 19 18 17 21 24 23 22 top view dip/soj a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 we v cc a 4 a 3 a 2 a 1 o 3 o 2 o 1 o 0 a 0 ce 11 12 19 18 a 8 v cc a 9 a 10 a 11 a 12 a 13 a 14 a 15 i 0 a 4 a 3 a 2 a 1 a 0 i 3 i 2 o 3 o 1 gnd ce we top view lcc 12 13 input buffer 25 28 27 26 a 14 a 15 i 0 i 1 a 5 i 3 i 2 i 1 a 7 a 6 a 5 o 2 o 0 i 0 i 1 i 2 i 3 7c192 only a 0 a 9 c191 ? 1 c191 ? 2 c191 ? 3 selection guide 7C192-12 7c192-15 7c192-20 7c192-25 maximum access time (ns) 12 15 20 25 maximum operating current (ma) 155 145 135 115 maximum standby current (ma) 30 30 30 30
cy7c192 document #: 38-05047 rev. ** page 2 of 10 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ..................................... ? 65 c to +150 c ambient temperature with power applied .................................................. ? 55 c to +125 c supply voltage to ground potential (pin 28 to pin 14) .................................................? 0.5v to +7.0v dc voltage applied to outputs in high z state [1] ....................................... ? 0.5v to v cc + 0.5v dc input voltage [1] .................................... ? 0.5v to v cc + 0.5v output current into outputs (low)............................. 20 ma static discharge voltage .......................................... >2001v (per mil-std-883, method 3015) latch-up current.................................................... >200 ma operating range range ambient temperature [2] v cc commercial 0 c to +70 c 5v 10% electrical characteristics over the operating range 7C192-12 7c192-15 parameter description test conditions min. max. min. max. unit v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.2 v cc +0.3v 2.2 v cc +0.3v v v il input low voltage [1] ? 0.5 0.8 ? 0.5 0.8 v i ix input load current gnd < v i < v cc ? 5+5 ? 5+5 a i oz output leakage current gnd < v o < v cc , output disabled ? 5+5 ? 5+5 a i os output short circuit current [3] v cc = max., v out = gnd ? 300 ? 300 ma i cc v cc operating supply current v cc = max. , i out = 0 ma, f = f max = 1/t rc 155 145 ma i sb1 automatic ce power- down current ? ttl inputs max. v cc , ce > v ih , v in > v ih or v in < v il , f = f max 30 30 ma i sb2 automatic ce power- down current ? cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v, f = 0 10 10 ma notes: 1. minimum voltage is equal to ? 2.0v for pulse durations of less than 20 ns. 2. t a is the case temperature. 3. not more than 1 output should be shorted at one time. duration of the short circuit should not exceed 30 seconds. cy7c192 document #: 38-05047 rev. ** page 3 of 10 electrical characteristics over the operating range parameter description test conditions 7c192-20 7c192-25 min. max. min. max. unit v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.2 v cc +0.3v 2.2 v cc +0.3v v v il input low voltage [1] ? 0.5 0.8 ? 3.0 0.8 v i ix input load current gnd < v i < v cc ? 5+5 ? 5+5 a i oz output leakage current gnd < v o < v cc , output disabled ? 5+5 ? 5+5 a i os output short circuit current [3] v cc = max., v out = gnd ? 300 ? 300 ma i cc v cc operating supply current v cc = max. , i out = 0 ma, f = f max = 1/t rc 135 115 ma i sb1 automatic ce power-down current ? ttl inputs max. v cc , ce > v ih , v in > v ih or v in < v il , f = f max 30 30 ma i sb2 automatic ce power-down current ? cmos inputs ce > v cc ? 0.3v, v in v cc ? 0.3v or v in < 0.3v, f = 0 15 15 ma capacitance [4] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 8 pf c out output capacitance 10 pf ac test loads and waveforms [5] notes: 4. tested initially and after any design or process changes that may affect these parameters. 5. t r = < 3 ns for the -12 and -15 speeds. t. r = < 5 ns for the -20 and slower speeds. 3.0v 5v output r1 481 ? r2 255 ? 30 pf including jig and scope gnd 90% 10% 90% 10% cy7c192 document #: 38-05047 rev. ** page 5 of 10 switching waveforms notes: 10. we is high for read cycle. 11. device is continuously selected, ce = v il . 12. address valid prior to or coincident with ce transition low. address data out previous data valid data valid t rc t aa t oha c191 ? 6 read cycle no. 1 [10, 11] 50% 50% data valid t rc t ace t lzce t pu data out high impedance impedance icc isb t hzce t pd ce high v cc supply current c191 ? 7 read cycle no. 2 [10, 12] t wc data valid data undefined high impedance t sce t aw t sa t pwe t ha t hd t hzwe t lzwe t sd ce we data in data out address c191 ? 8 write cycle no. 1 (we controlled) [9] cy7c192 document #: 38-05047 rev. ** page 6 of 10 notes: 13. if ce goes high simultaneously with we high, the output remains in a high-impedance state. switching waveforms (continued) t wc data valid t sce t aw t sa t pwe t ha t hd t sd high impedance t hzwe address ce we data in data out (7c192) c191 ? 9 write cycle no. 2 (ce controlled) [9, 13] cy7c192 document #: 38-05047 rev. ** page 7 of 10 typical dc and ac characteristics 1.2 1.4 1.0 0.6 0.4 0.2 4.0 4.5 5.0 5.5 6.0 1.6 1.4 1.2 1.0 0.8 -55 25 125 -55 25 125 1.2 1.0 0.8 normalized t aa 120 100 80 60 40 20 0.0 1.0 2.0 3.0 4.0 output source current (ma) supply voltage (v) normalized supply current vs. supply voltage normalized access time vs. ambient temperature ambient temperature ( c) normalized supply current vs. ambient temperature ambient temperature( c) output voltage (v) output source current vs. output voltage 0.0 0.8 1.4 1.1 1.0 0.9 4.0 4.5 5.0 5.5 6.0 normalized t supply voltage (v) normalized access time vs. supply voltage 120 140 100 60 40 20 0.0 1.0 2.0 3.0 4.0 output sink current (ma) 0 80 output voltage (v) output sink current vs. output voltage 0.6 0.4 0.2 0.0 normalized i, i cc sb normalized i, i cc sb i sb i cc i cc v cc =5.0v v cc =5.0v t a =25 c v cc =5.0v t a =25 c i sb t a =25 c 0.6 0.8 0 aa 1.3 1.2 v in =5.0v t a =25 c 1.4 v cc =5.0v v in =5.0v 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.0 2.0 3.0 4.0 normalized i po supply voltage (v) typical power-on current vs. supply voltage 30.0 25.0 20.0 15.0 10.0 5.0 0 200 400 600 800 delta t (ns) aa capacitance (pf) typical access time change vs. output loading 1.25 1.00 0.75 10 20 30 40 normalized i cc cycle frequency (mhz) normalized i cc vs. cycle time 0.0 5.0 0.0 1000 0.50 v cc =4.5v t a =25 c v cc =5.0v t a =25 c v in =0.5v cy7c192 document #: 38-05047 rev. ** page 8 of 10 ordering information speed (ns) ordering code package name package type operating range 12 cy7C192-12pc p21 28-lead (300-mil) molded dip commercial cy7C192-12vc v21 28-lead molded soj 15 cy7c192-15pc p21 28-lead (300-mil) molded dip commercial cy7c192-15vc v21 28-lead molded soj 20 cy7c192-20pc p21 28-lead (300-mil) molded dip commercial cy7c192-20vc v21 28-lead molded soj 25 cy7c192-25pc p21 28-lead (300-mil) molded dip commercial cy7c192-25vc v21 28-lead molded soj cy7c192 document #: 38-05047 rev. ** page 9 of 10 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagrams 51-85014-b 28-lead (300-mil) molded dip p21 28-lead (300-mil) molded soj v21 51-85031-b cy7c192 document #: 38-05047 rev. ** page 10 of 10 document title: cy7c192 64k x 4 static ram with separate i/o document number: 38-05047 rev. ecn no. issue date orig. of change description of change ** 107149 09/10/01 szv change spec number from: 38-00076 to 38-05047 |
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